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preliminary 18-mbit (512k x 36/1m x 18) flow-through sram cy7c1381d cy7c1383d cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-05544 rev. *a revised november 2, 2004 features ? supports 133-mhz bus operations ? 512k 36/1m 18 common i/o ? 3.3v ?5% and +10% core power supply (v dd ) ? 2.5v or 3.3v i/o supply (v ddq ) ? fast clock-to-output time ? 6.5 ns (133-mhz version) ? 8.5 ns (100-mhz version) ? provide high-performance 2-1-1-1 access rate ? user-selectable burst counter supporting intel ? pentium ? interleaved or linear burst sequences ? separate processor and controller address strobes ? synchronous self-timed write ? asynchronous output enable ? offered in jedec-standard lead-free 100-pin tqfp ,119-ball bga and 165-ball fbga packages ? jtag boundary scan for bga and fbga packages ? ?zz? sleep mode option functional description [1] the cy7c1381d/cy7c1383d is a 3.3v, 512k x 36 and 1 mbit x 18 synchronous flow-through srams, respectively designed to interface with high-speed microprocessors with minimum glue logic. maximum a ccess delay from clock rise is 6.5 ns (133-mhz version). a 2-bi t on-chip counter captures the first address in a burst and increments the address automati- cally for the rest of the burst access. all synchronous inputs are gated by registers controlle d by a positive-edge-triggered clock input (clk). the synchronous inputs include all addresses, all data inputs, address-pipelining chip enable ( ce 1 ), depth-expansion chip enables (ce 2 and ce 3 [2] ), burst control inputs ( adsc , adsp , and adv ), write enables ( bw x , and bwe ), and global write ( gw ). asynchronous inputs include the output enable ( oe ) and the zz pin . the cy7c1381d/cy7c1383d allows either interleaved or linear burst sequences, selected by the mode input pin. a high selects an interleaved burst sequence, while a low selects a linear burst sequence. burst accesses can be initiated with the proces sor address strobe (adsp ) or the cache controller address strobe (adsc ) inputs. address advancement is controlled by the address advancement (adv ) input. addresses and chip enables are registered at rising edge of clock when either address strobe processor ( adsp ) or address strobe controller ( adsc ) are active. subsequent burst addresses can be internally generated as controlled by the advance pin ( adv ). the cy7c1381d/cy7c1383d operates from a +3.3v core power supply while all outputs may operate with either a +2.5 or +3.3v supply. all inputs and outputs are jedec-standard jesd8-5-compatible. selection guide 133 mhz 100 mhz unit maximum access time 6.5 8.5 ns maximum operating current 210 175 ma maximum cmos standby current 70 70 ma notes: 1. for best?practices recommendations, please refer to the cypress application note system design guidelines on www.cypress.com. 2. ce 3, ce 2 are for tqfp and 165 fbga package only. 119 bga is offered only in 1 chip enable.
preliminary cy7c1381d cy7c1383d document #: 38-05544 rev. *a page 2 of 29 1 address register burst counter and logic clr q1 q0 enable register sense amps output buffers input registers memory array mode a [1:0] zz dq s dqp a dqp b dqp c dqp d a 0, a1, a adv clk adsp adsc bw d bw c bw b bw a bwe ce1 ce2 ce3 oe gw sleep control dq a , dqp a byte write register dq b , dqp b byte write register dq c , dqp c byte write register byte write register dq d , dqp d byte write register dq d , dqp d byte write register dq c , dqp c byte write register dq b , dqp b byte write register dq a , dqp a byte write register logic block diagram ? cy7c1381d (512k x 36) 2 address register adv clk burst counter and logic clr q1 q0 adsc ce 1 oe sense amps memory array adsp output buffers input registers mode ce 2 ce 3 gw bwe a 0,a1,a bw b bw a dq b ,dqp b write register dq a ,dqp a write register enable register a[1:0] dqs dqp a dqp b dq b ,dqp b write driver dq a ,dqp a write driver sleep control zz logic block diagram ? cy7c1383d (1 mbit x 18)
preliminary cy7c1381d cy7c1383d document #: 38-05544 rev. *a page 3 of 29 pin configurations a a a a a 1 a 0 nc nc v ss v dd a a a a a a a a dqp b dq b dq b v ddq v ssq dq b dq b dq b dq b v ssq v ddq dq b dq b v ss nc v dd zz dq a dq a v ddq v ssq dq a dq a dq a dq a v ssq v ddq dq a dq a dqp a dqp c dq c dq c v ddq v ssq dq c dq c dq c dq c v ssq v ddq dq c dq c v dd nc v ss dq d dq d v ddq v ssq dq d dq d dq d dq d v ssq v ddq dq d dq d dqp d a a ce 1 ce 2 bw d bw c bw b bw a ce 3 v dd v ss clk gw bwe oe adsc adsp adv a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 mode cy7c1381d (512k x 36) v ss /dnu a a a a a 1 a 0 nc nc v ss v dd a a a a a a a a a nc nc v ddq v ssq nc dqp a dq a dq a v ssq v ddq dq a dq a v ss nc v dd zz dq a dq a v ddq v ssq dq a dq a nc nc v ssq v ddq nc nc nc nc nc nc v ddq v ssq nc nc dq b dq b v ssq v ddq dq b dq b v dd nc v ss dq b dq b v ddq v ssq dq b dq b dqp b nc v ssq v ddq nc nc nc a a ce 1 ce 2 nc nc bw b bw a ce 3 v dd v ss clk gw bwe oe adsc adsp adv a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 mode cy7c1383d (1m x 18) v ss /dnu 100-pin tqfp pinout a a
preliminary cy7c1381d cy7c1383d document #: 38-05544 rev. *a page 4 of 29 pin configurations (continued) 234567 1 a b c d e f g h j k l m n p r t u v ddq nc nc dqp c dq c dq d dq c dq d aa aa adsp v ddq aa dq c v ddq dq c v ddq v ddq v ddq dq d dq d nc nc v ddq v dd clk v dd v ss v ss v ss v ss v ss v ss v ss v ss nc nc nc nc tdo tck tdi tms nc nc nc v ddq v ddq v ddq aaa a a a a a a a a a0 a1 dq a dq c dq a dq a dq a dq b dq b dq b dq b dq b dq b dq b dq a dq a dq a dq a dq b v dd dq c dq c dq c v dd dq d dq d dq d dq d adsc nc ce 1 oe adv gw v ss v ss v ss v ss v ss v ss v ss v ss dqp a mode dqp d dqp b bw b bw c nc v dd nc bw a nc bwe bw d zz 2 34567 1 a b c d e f g h j k l m n p r t u v ddq nc nc nc dq b dq b dq b dq b aa aa adsp v ddq aa nc v ddq nc v ddq v ddq v ddq nc nc nc nc v ddq v dd clk v dd v ss v ss v ss v ss v ss v ss v ss v ss nc nc nc nc tdo tck tdi tms a a nc v ddq v ddq v ddq anca a a a a a a a a a0 a1 dq a dq b nc nc dq a nc dq a dq a nc nc dq a nc dq a nc dq a nc dq a v dd nc dq b nc v dd dq b nc dq b nc adsc nc ce 1 oe adv gw v ss v ss v ss v ss v ss v ss v ss v ss nc mode dqp b dqp a nc bw b nc v dd nc bw a nc bwe nc zz cy7c1383d (1m x 18) cy7c1381d (512k x 36) 119-ball bga (1 chip enable with jtag)
preliminary cy7c1381d cy7c1383d document #: 38-05544 rev. *a page 5 of 29 pin configurations (continued) 165-ball fbga (3 chip enable) cy7c1381d (512k x 36) 234 567 1 a b c d e f g h j k l m n p r tdo nc / 288m nc dqp c dq c dqp d nc dq d ce 1 bw b ce 3 bw c bwe a ce 2 dq c dq d dq d mode nc dq c dq c dq d dq d dq d nc / 36m nc / 72m v ddq bw d bw a clk gw v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck v ss tdi a a dq c v ss dq c v ss dq c dq c nc v ss v ss v ss v ss nc v ss a1 dq d dq d nc nc v ddq v ss tms 891011 a adv a adsc nc oe adsp a nc / 144m v ss v ddq nc dqp b v ddq v dd dq b dq b dq b nc dq b nc dq a dq a v dd v ddq v dd v ddq dq b v dd nc v dd dq a v dd v ddq dq a v ddq v dd v dd v ddq v dd v ddq dq a v ddq a a v ss a a a dq b dq b dq b zz dq a dq a dqp a dq a a v ddq a cy7c1383d (1m x 18) a0 a v ss 234 567 1 a b c d e f g h j k l m n p r tdo nc / 288m nc nc nc dqp b v ss dq b ace 1 nc ce 3 bw b bwe a ce 2 nc dq b dq b mode nc dq b dq b nc nc nc nc / 36m nc / 72m v ddq nc bw a clk gw v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss v ss v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck a0 v ss tdi a a dq b v ss nc v ss dq b nc nc v ss v ss v ss v ss nc v ss a1 dq b nc nc nc v ddq v ss tms 891011 a adv a adsc a oe adsp a nc / 144m v ss v ddq nc dqp a v ddq v dd nc dq a dq a nc nc nc dq a nc v dd v ddq v dd v ddq dq a v dd nc v dd nc v dd v ddq dq a v ddq v dd v dd v ddq v dd v ddq nc v ddq a a v ss a a a dq a nc nc zz dq a nc nc dq a a v ddq a a a
preliminary cy7c1381d cy7c1383d document #: 38-05544 rev. *a page 6 of 29 pin definitions name i/o description a 0 , a 1 , a input- synchronous address inputs used to select one of the address location s. sampled at the rising edge of the clk if adsp or adsc is active low, and ce 1 , ce 2 , and ce 3 [2] are sampled active. a [1:0] feed the 2-bit counter. bw a , bw b bw c , bw d input- synchronous byte write select inputs, active low . qualified with bwe to conduct byte writes to the sram. sampled on the rising edge of clk. gw input- synchronous global write enable input, active low . when asserted low on the rising edge of clk, a global write is conducted (all bytes are written, regardless of the values on bw [a:d] and bwe ). clk input- clock clock input . used to capture all synchronous inputs to the device. also used to increment the burst counter when adv is asserted low, during a burst operation. ce 1 input- synchronous chip enable 1 input, active low . sampled on the rising edge of clk. used in conjunction with ce 2 and ce 3 [2] to select/deselect the device. adsp is ignored if ce 1 is high. ce 1 is sampled only when a new external address is loaded. ce 2 input- synchronous chip enable 2 input, active high . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 3 [2] to select/deselect the device. ce 2 is sampled only when a new external address is loaded. ce 3 [2] input- synchronous chip enable 3 input, active low . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 2 to select/desel ect the device. ce 3 is sampled only when a new external address is loaded. oe input- asynchronous output enable, asynchronous input, active low . controls the direction of the i/o pins. when low, the i/o pins behave as outputs. when deasserted hi gh, i/o pins are tri-stated, and act as input data pins. oe is masked during the firs t clock of a read cycle when emerging from a deselected state. adv input- synchronous advance input signal, sampled on the rising edge of clk . when asserted, it automat- ically increments the address in a burst cycle. adsp input- synchronous address strobe from processor, sampled on the rising edge of clk, active low . when asserted low, addresses presented to the device are captured in the address registers. a [1:0] are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. asdp is ignored when ce 1 is deasserted high adsc input- synchronous address strobe from controller, sampled on the rising edge of clk, active low . when asserted low, addresses presented to the device are captured in the address registers. a [1:0] are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized . bwe input- synchronous byte write enable input, active low . sampled on the rising edge of clk. this signal must be asserted low to conduct a byte write. zz input- asynchronous zz ?sleep? input, active high . when asserted high places the device in a non-time-critical ?sleep? condition with data in tegrity preserved. for no rmal operation, this pin has to be low or left floating. zz pin has an internal pull-down. dq s i/o- synchronous bidirectional data i/o lines . as inputs, they feed into an on-chip data register that is triggered by the rising edge of clk. as output s, they deliver the data contained in the memory location specified by the addr esses presented during the previous clock rise of the read cycle. the direction of the pins is controlled by oe . when oe is asserted low, the pins behave as outputs. when high, dq s and dqp x are placed in a tri-state condition. the outputs are automatically tri-st ated during the data portion of a write sequence, during the first clock when emerging from a deselect ed state, and when the device is deselected, regardless of the state of oe . dqp x i/o- synchronous bidirectional data parity i/o lines. functionally, these signals are identical to dq s . during write sequences, dqp x is controlled by bw x correspondingly. mode input-static selects burst order . when tied to gnd selects linear burst sequence. when tied to v dd or left floating selects interleaved burst seque nce. this is a strap pin and should remain static during device operation. mode pin has an internal pull-up. v dd power supply power supply inputs to the core of the device . v ddq i/o power supply power supply for the i/o circuitry . v ss ground ground for the core of the device .
preliminary cy7c1381d cy7c1383d document #: 38-05544 rev. *a page 7 of 29 functional overview all synchronous inputs pass through input registers controlled by the rising edge of the clock. maximum access delay from the clock rise (t cdv ) is 6.5 ns (133-mhz device). the cy7c1381d/cy7c1383d supports secondary cache in systems utilizing either a linear or interleaved burst sequence. the interleaved burst order supports pentium ? and i486 processors. the linear burst sequence is suited for processors that utilize a linear burst s equence. the burst order is user-selectable, and is determined by sampling the mode input. accesses can be initiated with either the processor address strobe (adsp ) or the controller address strobe (adsc ). address advancement th rough the burst sequence is controlled by the adv input. a two-bit on-chip wraparound burst counter captures the firs t address in a burst sequence and automatically increments the address for the rest of the burst access. byte write operations are qualif ied with the byte write enable (bw e ) and byte write select (bwx ) inputs. a global write enable (gw ) overrides all byte write inputs and writes data to all four bytes. all writes are simplified with on-chip synchronous self-timed write circuitry. three synchronous chip selects (ce 1 , ce 2 , ce 3 [2] ) and an asynchronous output enable (oe ) provide for easy bank selection and output tri-state control. adsp is ignored if ce 1 is high. single read accesses a single read access is initiated when the following conditions are satisfied at clock rise: (1) ce 1 , ce 2 , and ce 3 [2] are all asserted active, and (2) adsp or adsc is asserted low (if the access is initiated by adsc , the write inputs must be deasserted during this first cycle). the address presented to the address inputs is latched into the address register and the burst counter/control logic and presented to the memory core. if the oe input is asserted low, the requested data will be available at the data outputs a maximum to tcdv after clock rise. adsp is ignored if ce 1 is high. single write accesses initiated by adsp this access is initiated when the following conditions are satisfied at cl ock rise: (1) ce 1 , ce 2 , ce 3 [2] are all asserted active, and (2) adsp is asserted low. the addresses presented are loaded into t he address register and the burst inputs (gw , bw e , and bw x )are ignored during this first clock cycle. if the write inputs are a sserted active ( see write cycle descriptions table for appropriate states that indicate a write) on the next clock rise,the appropriate data will be latched and written into the device.byte writes are allowed. all i/os are tri-stated during a byte write. since this is a common i/o device, the asynchronous oe input signal must be deasserted and the i/os must be tri-stated prior to the presentation of data to dqs. as a safety precaution, the data lines are tri-stated once a write cycle is detected, regardless of the state of oe . single write accesses initiated by adsc this write access is initiated when the following conditions are satisfied at clock rise: (1) ce 1 , ce 2 , and ce 3 [2] are all asserted active, (2) adsc is asserted low, (3) adsp is deasserted high, and (4) the write input signals (gw , bwe , and bw x ) indicate a write access. adsc is ignored if adsp is active low. the addresses presented are loaded into the address register and the burst counter/control logic and delivered to the memory core. the information presented to dq [a:d] will be written into the specified address location. byte writes are allowed. all i/os are tri-stated when a write is detected, even a byte write. since this is a common i/o device, the asynchronous oe input signal must be deasserted and the i/os must be tri-stated prior to the presentation of data to dqs. as a safety precaution, the data lines are tri-stated once a write cycle is detected, regardless of the state of oe . burst sequences the cy7c1381d/cy7c1383d provides an on-chip two-bit wraparound burst counter inside the sram. the burst counter is fed by a [1:0] , and can follow either a linear or interleaved burst order. the burst order is determined by the state of the mode input. a low on mode will select a linear burst sequence. a high on mode will select an interleaved burst v ssq i/o ground ground for the i/o circuitry . tdo jtag serial output synchronous serial data-out to the jtag circuit . delivers data on the negativ e edge of tck. if the jtag feature is not being utilized, this pin should be left unconnected. this pin is not available on tqfp packages. tdi jtag serial input synchronous serial data-in to the jtag circuit . sampled on the rising edge of tck. if the jtag feature is not being utilized, this pin can be left floating or connected to v dd through a pull up resistor. this pin is not available on tqfp packages. tms jtag serial input synchronous serial data-in to the jtag circuit . sampled on the rising edge of tck. if the jtag feature is not being utilized, this pin can be disconnected or connected to v dd . this pin is not available on tqfp packages. tck jtag- clock clock input to the jtag circuitry . if the jtag feature is not being utilized, this pin must be connected to v ss . this pin is not available on tqfp packages. nc ? no connects . not internally connected to the die. 36m, 72m, 144m and 288m are address expansion pins are not internally connected to the die. v ss /dnu ground/dnu this pin can be connected to ground or should be left floating. pin definitions (continued) name i/o description
preliminary cy7c1381d cy7c1383d document #: 38-05544 rev. *a page 8 of 29 order. leaving mode uncon nected will cause the device to default to a interleaved burst sequence. sleep mode the zz input pin is an asynchronous input. asserting zz places the sram in a power conservation ?sleep? mode. two clock cycles are required to enter into or exit from this ?sleep? mode. while in this mode, data integrity is guaranteed. accesses pending when entering the ?sleep? mode are not considered valid nor is the completion of the operation guaranteed. the device must be deselected prior to entering the ?sleep? mode. ce 1 , ce 2 , ce 3 [2] , adsp , and adsc must remain inactive for the duration of t zzrec after the zz input returns low. interleaved burst address table (mode = floating or v dd ) first address a1: a0 second address a1: a0 third address a1: a0 fourth address a1: a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = gnd) first address a1: a0 second address a1: a0 third address a1: a0 fourth address a1: a0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 zz mode electrical characteristics parameter description test conditions min. max. unit i ddzz sleep mode standby current zz > v dd ? 0.2v 80 ma t zzs device operation to zz zz > v dd ? 0.2v 2t cyc ns t zzrec zz recovery time zz < 0.2v 2t cyc ns t zzi zz active to sleep current t his parameter is sampled 2t cyc ns t rzzi zz inactive to exit sleep current this parameter is sampled 0 ns truth table [ 3, 4, 5, 6, 7] cycle description address used ce 1 ce 2 ce 3 zz adsp adsc adv write oe clk dq deselected cycle, power-down none h x x l x l x x x l-h tri-state deselected cycle, power-down none l l x l l x x x x l-h tri-state deselected cycle, power-down none l x h l l x x x x l-h tri-state deselected cycle, power-down none l l x l h l x x x l-h tri-state deselected cycle, power-down none x x x l h l x x x l-h tri-state sleep mode, power-down none x x x h x x x x x x tri-state read cycle, begin burst external l h l l l x x x l l-h q read cycle, begin burst external l h l l l x x x h l-h tri-state write cycle, begin burst external l h l l h l x l x l-h d notes: 3. x=?don't care.? h = logic high, l = logic low. 4. write = l when any one or more byte write enable signals and bwe = l or gw = l. write = h when all byte write enable signals , bwe , gw = h.. 5. the dq pins are controlled by the current cycle and the oe signal. oe is asynchronous and is not sampled with the clock. 6. the sram always initiates a read cycle when adsp is asserted, regardless of the state of gw , bwe , or bw x . writes may occur only on subsequent clocks after the adsp or with the assertion of adsc . as a result, oe must be driven high prior to the start of the write cycle to allow the outputs to tri-state. oe is a don't care for the remainder of the write cycle. 7. oe is asynchronous and is not sampled with the clock rise. it is masked internally during write cycles. during a read cycle all d ata bits are tri-state when oe is inactive or when the device is deselect ed, and all data bits behave as output when oe is active (low).
preliminary cy7c1381d cy7c1383d document #: 38-05544 rev. *a page 9 of 29 read cycle, begin burst external l h l l h l x h l l-h q read cycle, begin burst external l h l l h l x h h l-h tri-state read cycle, continue burst next x x x l h h l h l l-h q read cycle, continue burst next x x x l h h l h h l-h tri-state read cycle, continue burst next h x x l x h l h l l-h q read cycle, continue burst next h x x l x h l h h l-h tri-state write cycle, continue burst next x x x l h h l l x l-h d write cycle, continue burst next h x x l x h l l x l-h d read cycle, suspend burst current x x x l h h h h l l-h q read cycle, suspend burst current x x x l h h h h h l-h tri-state read cycle, suspend burst current h x x l x h h h l l-h q read cycle, suspend burst current h x x l x h h h h l-h tri-state write cycle, suspend burst current x x x l h h h l x l-h d write cycle, suspend burst current h x x l x h h l x l-h d truth table (continued) [ 3, 4, 5, 6, 7] cycle description address used ce 1 ce 2 ce 3 zz adsp adsc adv write oe clk dq partial truth table for read/write [3, 8] function (cy7c1381d) gw bwe bw d bw c bw b bw a read h h x x x x read hlhhhh write byte a (dq a , dqp a )hlhhhl write byte b(dq b , dqp b )hlhhlh write bytes a, b (dq a , dq b , dqp a , dqp b )h l h h l l write byte c (dq c , dqp c ) hlhlhh write bytes c, a (dq c , dq a, dqp c , dqp a )hlhlhl write bytes c, b (dq c , dq b, dqp c , dqp b )h l h l l h write bytes c, b, a (dq c , dq b , dq a, dqp c , dqp b , dqp a ) hlhlll write byte d (dq d , dqp d )hllhhh write bytes d, a (dq d , dq a, dqp d , dqp a )h l l h h l write bytes d, b (dq d , dq a, dqp d , dqp a )h l l h l h write bytes d, b, a (dq d , dq b , dq a, dqp d , dqp b , dqp a ) hllhll write bytes d, b (dq d , dq b, dqp d , dqp b )h l l l h h write bytes d, b, a (dq d , dq c , dq a, dqp d , dqp c , dqp a ) hlllhl write bytes d, c, a ( dq d , dq b , dq a, dqp d , dqp b , dqp a ) hllllh write all bytes hlllll write all bytes l x x x x x note: 8. table only lists a partial listing of the byte write combinations. any combination of bw x is valid appropriate write will be done bas ed on which byte write is active.
preliminary cy7c1381d cy7c1383d document #: 38-05544 rev. *a page 10 of 29 ieee 1149.1 serial boundary scan (jtag) the cy7c1381d/cy7c1383d incorporates a serial boundary scan test access port (tap) in the bga package only. the tqfp package does not offer this functionality. this part operates in accordance with ieee standard 1149.1-1900, but doesn?t have the set of functions required for full 1149.1 compliance. these functions fr om the ieee specification are excluded because their inclusion places an added delay in the critical speed path of the sram. note the tap controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant taps. the tap operates using jedec-standard 3. 3v or 2.5v i/o logic levels. the cy7c1381d/cy7c1383d contains a tap controller, instruction register, boundary sc an register, bypass register, and id register. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap controller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are inter- nally pulled up and may be unconnected. they may alternately be connected to v dd through a pull-up resistor. tdo should be left unconnected. upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. tap controller state diagram the 0/1 next to each state repr esents the value of tms at the rising edge of tck. test access port (tap) test clock (tck) the test clock is used only with the tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. it is allowable to leave this ball unconnected if the tap is not used. the ball is pulled up internally, resulting in a logic high level. test data-in (tdi) truth table for read/write [3,8] function (cy7c1383d) gw bwe bw b bw a read h h x x read h l h h write byte a ? ( dq a and dqp a )hlhl write byte b ? ( dq b and dqp b )hllh write all bytes h l l l write all bytes l x x x test-logic reset run-test/ idle select dr-scan select ir-scan capture-dr shift-dr capture-ir shift-ir exit1-dr pause-dr exit1-ir pause-ir exit2-dr update-dr exit2-ir update-ir 1 1 1 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0
preliminary cy7c1381d cy7c1383d document #: 38-05544 rev. *a page 11 of 29 tap controller block diagram performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this rese t does not affect the operation of the sram and may be performed while the sram is operating. at power-up, the tap is reset in ternally to ensure that tdo comes up in a high-z state. tap registers registers are connected between the tdi and tdo balls and allow data to be scanned into and out of the sram test circuitry. only one register can be selected at a time through the instruction register. data is serially loaded into the tdi ball on the rising edge of tck. data is output on the tdo ball on the falling edge of tck. instruction register three-bit instructions can be serially loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo balls as shown in the tap controller block diagram. upon power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as described in the previous section. when the tap controller is in the capture-ir state, the two least significant bits are loaded with a binary ?01? pattern to allow for fault isolation of the board-level serial test data path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between the tdi and tdo balls. this allows data to be shifted through the sram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and bidirectional balls on the sram. the boundary scan register is lo aded with the contents of the ram i/o ring when the tap controller is in the capture-dr state and is then placed betwe en the tdi and tdo balls when the controller is moved to the shift-dr state. the extest, sample/preload and sample z instructions can be used to capture the conten ts of the i/o ring. the boundary scan order tables show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction register. the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id register has a vendor code and other information described in the identification register definitions table. tap instruction set overview eight different instructions are possible with the three-bit instruction register. all combinations are listed in the instruction codes table. three of these instructions are listed as reserved and should not be used. the other five instruc- tions are described in detail below. the tap controller used in this sram is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. the tap controller cannot be used to load address data or control signals into the sram and cannot preload the i/o buffers. the sram does not implement the 1149.1 commands extest or intest or the preload portion of sample/preload; rather, it per forms a capture of the i/o ring when these instructions are executed. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this stat e, instructions are shifted through the instruction register through the tdi and tdo balls. to execute the instruction once it is shifted in, the tap controller needs to be moved into the update-ir state. extest extest is a mandatory 1149.1 instruction which is to be executed whenever the instructi on register is loaded with all 0s. extest is not implemented in this sram tap controller, and therefore this device is not compliant to 1149.1. the tap controller does recognize an all-0 instruction. when an extest instruction is loaded into the instruction register, the sram responds as if a sample/preload instruction has been loaded. there is one difference between the two instructions. un like the sample/preload instruction, extest places the sram outputs in a high-z state. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo balls and allows the idcode to be shifted out of the device when the tap controller enters the shift-dr state. bypass register 0 instruction register 0 1 2 identification register 0 1 2 29 30 31 . . . boundary scan register 0 1 2 . . x . . . s election circuitr y selection circuitry tck t ms tap controller tdi td o
preliminary cy7c1381d cy7c1383d document #: 38-05544 rev. *a page 12 of 29 the idcode instruction is loaded into the instruction register upon power-up or whenever the tap controller is given a test logic reset state. sample z the sample z instruction caus es the boundary scan register to be connected between the tdi and tdo balls when the tap controller is in a shift-dr state. it also places all sram outputs into a high-z state. sample/preload sample/preload is a 1149.1 mandatory instruction. when the sample/preload instructi ons are loaded into the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. the user must be aware that th e tap controller clock can only operate at a frequency up to 20 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possible that during the captur e-dr state, an input or output will undergo a transition. the tap may then try to capture a signal while in transition (metastable state). this will not harm the device, but there is no guar antee as to the value that will be captured. repeatable results may not be possible. to guarantee that the boundary scan register will capture the correct value of a signal, the sram signal must be stabilized long enough to meet the tap controller's capture set-up plus hold times (t cs and t ch ). the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample/p reload instruction. if this is an issue, it is still possible to capture all other signals and simply ignore the value of the ck and ck# captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo pins. preload allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation. the shifting of data for the sample and preload phases can occur concurrently when required - that is, while data captured is shifted out, the pr eloaded data can be shifted in. bypass when the bypass instruction is loaded in t he instruction register and the tap is placed in a shift-dr state, the bypass register is placed between the tdi and tdo balls. the advantage of the bypass instructio n is that it shortens the boundary scan path when multiple devices are connected together on a board. reserved these instructions are not im plemented but are reserved for future use. do not use these instructions. tap timing t tl test clock (tck) 123456 t est mode select (tms) t th test data-out (tdo) t cyc test data-in (tdi) t tmsh t tmss t tdih t tdis t tdox t tdov don?t care undefined
preliminary cy7c1381d cy7c1383d document #: 38-05544 rev. *a page 13 of 29 3.3v tap ac test conditions input pulse levels ................................................ v ss to 3.3v input rise and fall times ......... .......................................... 1 ns input timing referenc e levels ...........................................1.5v output reference levels...................................................1.5v test load termination supply vo ltage...............................1.5v 3.3v tap ac output load equivalent 2.5v tap ac test conditions input pulse levels ......................................... v ss to 2.5v input rise and fall time .....................................................1 ns input timing reference levels... ...................................... 1.25v output reference levels .......... ...................................... 1.25v test load termination supply voltage ............................ 1.25v 2.5v tap ac output load equivalent notes: 9. t cs and t ch refer to the setup and hold time requirements of latching data from the boundary scan register. 10. test conditions are specified using th e load in tap ac test conditions. t r /t f = 1ns tap ac switching characteristics over the operating range [9, 10] parameter description min. max. unit clock t tcyc tck clock cycle time 50 ns t tf tck clock frequency 20 mhz t th tck clock high time 25 ns t tl tck clock low time 25 ns output times t tdov tck clock low to tdo valid 5 ns t tdox tck clock low to tdo invalid 0 ns set-up times t tmss tms set-up to tck clock rise 5 ns t tdis tdi set-up to tck clock rise 5 ns t cs capture set-up to tck rise 5 hold times t tmsh tms hold after tck clock rise 5 ns t tdih tdi hold after clock rise 5 ns t ch capture hold after clock rise 5 ns t do 1.5v 20p f z = 50 ? o 50 ? t do 1.25v 20p f z = 50 ? o 50 ?
preliminary cy7c1381d cy7c1383d document #: 38-05544 rev. *a page 14 of 29 notes: 11. all voltages referenced to v ss (gnd). 12. bit #24 is ?1? in the register definitions fo r both 2.5v and 3.3v versions of this device. tap dc electrical characteristics and operating conditions (0c < ta < +70c; vdd = 3.3v 0.165v unless otherwise noted) [11] parameter description conditions min. max. unit v oh1 output high voltage i oh = ?4.0 ma v ddq = 3.3v 2.4 v i oh = ?1.0 ma v ddq = 2.5v 2.0 v v oh2 output high voltage i oh = ?100 a v ddq = 3.3v 2.9 v v ddq = 2.5v 2.1 v v ol1 output low voltage i ol = 8.0 ma v ddq = 3.3v 0.4 v i ol = 8.0 ma v ddq = 2.5v 0.4 v v ol2 output low voltage i ol = 100 a v ddq = 3.3v 0.2 v v ddq = 2.5v 0.2 v v ih input high voltage v ddq = 3.3v 2.0 v dd + 0.3 v v ddq = 2.5v 1.7 v dd + 0.3 v v il input low voltage v ddq = 3.3v ?0.3 0.8 v v ddq = 2.5v ?0.3 0.7 v i x input load current gnd < v in < v ddq -5 5 a identification register definitions instruction field cy7c1381d (512k 36) cy7c1383d (1m 18) description revision number (31:29) 000 000 describes the version number. device depth (28:24) [12] 01011 01011 reserved for internal use device width (23:18) 000001 000001 defines memory type and architecture cypress device id (17:12) 100101 010101 defines width and density cypress jedec id code (11:1) 00000110100 00000110100 allows unique identification of sram vendor. id register presence indicator (0) 11 indicates the presence of an id register. scan register sizes register name bit size (36) bit size (18) instruction bypass 33 bypass 11 id 32 32 boundary scan order (119-ball bga package) 85 85 boundary scan order (165-ball fbga package) 89 89
preliminary cy7c1381d cy7c1383d document #: 38-05544 rev. *a page 15 of 29 identification codes instruction code description extest 000 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all sram outputs to high-z state. idcode 001 loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operations. sample z 010 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all sram output drivers to a high-z state. reserved 011 do not use: this instruction is reserved for future use. sample/preload 100 captures i/o ring contents. places the boundary scan register between tdi and tdo. does not affect sram operation. reserved 101 do not use: this instruction is reserved for future use. reserved 110 do not use: this instruction is reserved for future use. bypass 111 places the bypass register between tdi and td o. this operation do es not affect sram operations.
preliminary cy7c1381d cy7c1383d document #: 38-05544 rev. *a page 16 of 29 119-ball bga boundary scan order [13, 14] cy7c1381d (256k 36) cy7c1383d (512k 18) bit# ball id bit# ball id bit# ball id bit# ball id 1 h4 44 e4 1 h4 44 e4 2t445 g4 2 t4 45 g4 3t546 a4 3 t5 46 a4 4t647 g3 4 t6 47 g3 5 r5 48 c3 5 r5 48 c3 6 l5 49 b2 6 l5 49 b2 7r650 b3 7 r6 50 b3 8u651 a3 8 u6 51 a3 9 r7 52 c2 9 r7 52 c2 10 t7 53 a2 10 t7 53 a2 11 p6 54 b1 11 p6 54 b1 12 n7 55 c1 12 n7 55 c1 13 m6 56 d2 13 m6 56 d2 14 l7 57 e1 14 l7 57 e1 15 k6 58 f2 15 k6 58 f2 16 p7 59 g1 16 p7 59 g1 17 n6 60 h2 17 n6 60 h2 18 l6 61 d1 18 l6 61 d1 19 k7 62 e2 19 k7 62 e2 20 j5 63 g2 20 j5 63 g2 21 h6 64 h1 21 h6 64 h1 22 g7 65 j3 22 g7 65 j3 23 f6 66 k2 23 f6 66 k2 24 e7 67 l1 24 e7 67 l1 25 d7 68 m2 25 d7 68 m2 26 h7 69 n1 26 h7 69 n1 27 g6 70 p1 27 g6 70 p1 28 e6 71 k1 28 e6 71 k1 29 d6 72 l2 29 d6 72 l2 30 c7 73 n2 30 c7 73 n2 31 b7 74 p2 31 b7 74 p2 32 c6 75 r3 32 c6 75 r3 33 a6 76 t1 33 a6 76 t1 34 c5 77 r1 34 c5 77 r1 35 b5 78 t2 35 b5 78 t2 36 g5 79 l3 36 g5 79 l3 37 b6 80 r2 37 b6 80 r2 38 d4 81 t3 38 d4 81 t3 39 b4 82 l4 39 b4 82 l4 40 f4 83 n4 40 f4 83 n4 41 m4 84 p4 41 m4 84 p4 42 a5 85 internal 42 a5 85 internal 43 k4 43 k4 notes: 13. balls that are nc (no connect) are pre-set low. 14. bit# 85 is pre-set high.
preliminary cy7c1381d cy7c1383d document #: 38-05544 rev. *a page 17 of 29 165-ball bga boundary scan order [13, 15] cy7c1381d (256k x 36) cy7c1381d (256kx36) bit# ball id bit# ball id bit# ball id 1n637 a9 73 k2 2n738 b9 74 l2 3 10n 39 c10 75 m2 4p1140 a8 76 n1 5p841 b8 77 n2 6r842 a7 78 p1 7r943 b7 79 r1 8p944 b6 80 r2 9 p10 45 a6 81 p3 10 r10 46 b5 82 r3 11 r11 47 a5 83 p2 12 h11 48 a4 84 r4 13 n11 49 b4 85 p4 14 m11 50 b3 86 n5 15 l11 51 a3 87 p6 16 k11 52 a2 88 r6 17 j11 53 b2 89 internal 18 m10 54 c2 19 l10 55 b1 20 k10 56 a1 21 j10 57 c1 22 h9 58 d1 23 h10 59 e1 24 g11 60 f1 25 f11 61 g1 26 e11 62 d2 27 d11 63 e2 28 g10 64 f2 29 f10 65 g2 30 e10 66 h1 31 d10 67 h3 32 c11 68 j1 33 a11 69 k1 34 b11 70 l1 35 a10 71 m1 36 b10 72 j2 note: 15. bit# 89 is pre-set high.
preliminary cy7c1381d cy7c1383d document #: 38-05544 rev. *a page 18 of 29 165-ball bga boundary scan order [13, 15] cy7c1383d (512k x 18) cy7c1383d (512kx18) bit# ball id bit# ball id bit# ball id 1n637a9 73 k2 2n738b9 74 l2 3 10n 39 c10 75 m2 4p1140a8 76 n1 5p841b8 77 n2 6r842a7 78 p1 7r943b7 79 r1 8p944b6 80 r2 9 p10 45 a6 81 p3 10 r10 46 b5 82 r3 11 r11 47 a5 83 p2 12 h11 48 a4 84 r4 13 n11 49 b4 85 p4 14 m11 50 b3 86 n5 15 l11 51 a3 87 p6 16 k11 52 a2 88 r6 17 j11 53 b2 89 internal 18 m10 54 c2 19 l10 55 b1 20 k10 56 a1 21 j10 57 c1 22 h9 58 d1 23 h10 59 e1 24 g11 60 f1 25 f11 61 g1 26 e11 62 d2 27 d11 63 e2 28 g10 64 f2 29 f10 65 g2 30 e10 66 h1 31 d10 67 h3 32 c11 68 j1 33 a11 69 k1 34 b11 70 l1 35 a10 71 m1 36 b10 72 j2
preliminary cy7c1381d cy7c1383d document #: 38-05544 rev. *a page 19 of 29 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ............. .............. ...... ?65c to +150c ambient temperature with power applied........... .............. .............. ...... ?55c to +125c supply voltage on v dd relative to gnd........ ?0.3v to +4.6v dc voltage applied to outputs in tri-state........................................... ?0.5v to v ddq + 0.5v dc input voltage....................................?0.5v to v dd + 0.5v current into outputs (low).... ..................................... 20 ma static discharge voltage......... ........... ............ .......... > 2001v (per mil-std-883, method 3015) latch-up current.................................................... > 200 ma operating range range ambient temperature v dd v ddq commercial 0c to +70c 3.3v ? 5%/+10% 2.5v ? 5% to v dd industrial ?40c to +85c electrical characteristics over the operating range [16, 17] parameter description test conditions min. max. unit v dd power supply voltage 3.135 3.6 v v ddq i/o supply voltage v ddq = 3.3v 3.135 v dd v v ddq = 2.5v 2.375 2.625 v v oh output high voltage v ddq = 3.3v, v dd = min., i oh = ?4.0 ma 2.4 v v ddq = 2.5v, v dd = min., i oh = ?1.0 ma 2.0 v v ol output low voltage v ddq = 3.3v, v dd = min., i ol = 8.0 ma 0.4 v v ddq = 2.5v, v dd = min., i ol = 1.0 ma 0.4 v v ih input high voltage [16] v ddq = 3.3v 2.0 v dd + 0.3v v v ddq = 2.5v 1.7 v dd + 0.3v v v il input low voltage [16] v ddq = 3.3v ?0.3 0.8 v v ddq = 2.5v ?0.3 0.7 v i x input load gnd v i v ddq ?5 5 a input current of mode input = v ss ?5 a input = v dd 30 a input current of zz input = v ss ?30 a input = v dd 5 a i oz output leakage current gnd v i v dd, output disabled ?5 5 a i dd v dd operating supply current v dd = max., i out = 0 ma, f = f max = 1/t cyc 7.5-ns cycle, 133 mhz 210 ma 10-ns cycle, 100 mhz 175 ma i sb1 automatic ce power-down current?ttl inputs max. v dd , device deselected, v in v ih or v in v il , f = f max, inputs switching 7.5-ns cycle, 133 mhz 140 ma 10-ns cycle, 100 mhz 120 i sb2 automatic ce power-down current?cmos inputs max. v dd , device deselected, v in v dd ? 0.3v or v in 0.3v, f = 0, inputs static all speeds 70 ma i sb3 automatic ce power-down current?cmos inputs max. v dd , device deselected, v in v ddq ? 0.3v or v in 0.3v, f = f max , inputs switching 7.5-ns cycle, 133 mhz 130 ma 10-ns cycle, 100 mhz 110 ma i sb4 automatic ce power-down current?ttl inputs max. v dd , device deselected, v in v dd ? 0.3v or v in 0.3v, f = 0, inputs static all speeds 80 ma notes: 16. overshoot: v ih (ac) < v dd +1.5v (pulse width less than t cyc /2), undershoot: v il (ac) > -2v (pulse width less than t cyc /2). 17. t power-up : assumes a linear ramp from 0v to v dd (min.) within 200ms. during this time v ih < v dd and v ddq < v dd
preliminary cy7c1381d cy7c1383d document #: 38-05544 rev. *a page 20 of 29 thermal resistance [18] parameter description test conditions tqfp package bga package fbga package unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedence, per eia / jesd51. 31 45 46 c/w jc thermal resistance (junction to case) 673c/w capacitance [18] parameter description test conditions tqfp package bga package fbga package unit c in input capacitance t a = 25c, f = 1 mhz, v dd = 3.3v. v ddq = 2.5v 589pf c clk clock input capacitance 5 8 9 pf c i/o input/output capacitance 5 8 9 pf ac test loads and waveforms switching characteristics over the operating range [20, 21] parameter description 133 mhz 100 mhz unit min. max. min. max. t power v dd (typical) to the first access [19] 11ms clock t cyc clock cycle time 7.5 10 ns t ch clock high 2.1 2.5 ns t cl clock low 2.1 2.5 ns output times t cdv data output valid after clk rise 6.5 8.5 ns t doh data output hold after clk rise 2.0 2.0 ns t clz clock to low-z [20, 21, 22] 2.0 2.0 ns t chz clock to high-z [20, 21, 22] 0 4.0 0 5.0 ns t oev oe low to output valid 3.2 3.8 ns t oelz oe low to output low-z [20, 21, 22] 00ns t oehz oe high to output high-z [20, 21, 22] 4.0 5.0 ns setup times t as address set-up befo re clk rise 1.5 1.5 ns output r = 317 ? r = 351 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.5v 3.3v all input pulses v ddq gnd 90% 10% 90% 10% 1ns 1ns (c) output r = 1667 ? r =1538 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.25v 2.5v all input pulses v ddq gnd 90% 10% 90% 10% 1ns 1ns (c) 3.3v i/o test load 2.5v i/o test load
preliminary cy7c1381d cy7c1383d document #: 38-05544 rev. *a page 21 of 29 t ads adsp , adsc set-up before clk rise 1.5 1.5 ns t advs adv set-up before clk rise 1.5 1.5 ns t wes gw , bwe , bw [a:d] set-up before clk rise 1.5 1.5 ns t ds data input set-up before clk rise 1.5 1.5 ns t ces chip enable set-up 1.5 1.5 ns hold times t ah address hold after clk rise 0.5 0.5 ns t adh adsp , adsc hold after clk rise 0.5 0.5 ns t weh gw , bwe , bw [a:d] hold after clk rise 0.5 0.5 ns t advh adv hold after clk rise 0.5 0.5 ns t dh data input hold after clk rise 0.5 0.5 ns t ceh chip enable hold after clk rise 0.5 0.5 ns notes: 18. tested initially and after any design or process change that may affect these parameters. 19. this part has a voltage regulator internally; t power is the time that the power needs to be supplied above v dd ( minimum) initially, before a read or write operation can be initiated. 20. t chz , t clz ,t oelz , and t oehz are specified with ac test conditions shown in part (b) of ac test loads. transition is measured 200 mv from steady-state vo ltage. 21. at any given voltage and temperature, t oehz is less than t oelz and t chz is less than t clz to eliminate bus contention betw een srams when sharing the same data bus. these specifications do not imply a bus contention condition, but refl ect parameters guaranteed over worst case user conditions. device is designed to achieve high-z prior to low-z under the same system conditions switching characteristics over the operatin g range (continued) [20, 21] parameter description 133 mhz 100 mhz unit min. max. min. max.
preliminary cy7c1381d cy7c1383d document #: 38-05544 rev. *a page 22 of 29 timing diagrams read cycle timing [25] note: 22. this parameter is sampled and not 100% tested. t cyc t cl clk t adh t ads address t ch t ah t as a1 t ceh t ces data out (q) high-z t clz t doh t cdv t oehz t cdv single read burst read t oev t oelz t chz burst wraps around to its initial state t advh t advs t weh t wes t adh t ads q(a2) q(a2 + 1) q(a2 + 2) q(a1) q(a2) q(a2 + 1) q(a2 + 2) q(a2 + 3) a2 adv suspends burst deselect cycle don?t care undefined adsp adsc g w, bwe,bw x ce adv oe
preliminary cy7c1381d cy7c1383d document #: 38-05544 rev. *a page 23 of 29 3 write cycle timing [25, 26] notes: 23. timing reference level is 1.5v when v ddq = 3.3v and is 1.25v when v ddq = 2.5v. 24. test conditions shown in (a) of ac test loads unless otherwise noted. timing diagrams (continued) t cyc t cl clk t adh t ads address t ch t ah t as a1 t ceh t ces high-z burst read burst write d(a2) d(a2 + 1) d(a2 + 1) d(a1) d(a3) d(a3 + 1) d(a3 + 2) d(a2 + 3) a2 a3 extended burst write d(a2 + 2) single write t adh t ads t adh t ads t oehz t advh t advs t weh t wes t dh t ds t weh t wes byte write signals are ignored for first cycle when adsp initiates burst adsc extends burst adv suspends burst don?t care undefined adsp adsc bwe, bw x gw ce adv oe data in (d) d ata out (q)
preliminary cy7c1381d cy7c1383d document #: 38-05544 rev. *a page 24 of 29 read/write cycle timing [25, 27, 28] notes: 25. on this diagram, when ce is low: ce 1 is low, ce 2 is high and ce 3 is low. when ce is high: ce 1 is high or ce 2 is low or ce 3 is high. 26. full width write can be initiated by either gw low; or by gw high, bwe low and bw x low. 27. the data bus (q) remains in high-z following a write cycle, unless a new read ac cess is initiated by adsp or adsc . 28. gw is high. timing diagrams (continued) t cyc t cl clk t adh t ads address t ch t ah t as a2 t ceh t ces single write d(a3) a3 a4 burst read back-to-back reads high-z q(a2) q(a4) q(a4+1) q(a4+2) q(a4+3) t weh t wes t oehz t dh t ds t cdv t oelz a1 a5 a6 d(a5) d(a6) q(a1) back-to-back writes don?t care undefined adsp adsc bwe, bw x ce adv oe data in (d) d ata out (q)
preliminary cy7c1381d cy7c1383d document #: 38-05544 rev. *a page 25 of 29 timing diagrams (continued) t zz i supply clk zz t zzrec a ll inputs (except zz) don?t care i ddzz t zzi t rzzi outputs (q) high-z deselect or read only z z mode timing [29 , 30] ordering information speed (mhz) ordering code package name part and package type operating range 133 cy7c1381d-133axc cy7c1383d-133axc a101 lead-free 100-lead thin quad flat pack (14 x 20 x 1.4mm) 3 chip enables commercial cy7c1381d-133bgc CY7C1383D-133BGC bg119 119-ball (14 x 22 x 2.4 mm) bga 3 chip enables and jtag cy7c1381d-133bzc cy7c1383d-133bzc bb165d 165-ball fine-pitch ball grid array (13 x 15 x 1.4mm) 3 chip enables and jtag cy7c1381d-133bgxc cy7c1383d-133bgxc bg119 lead-free 119-ball (14 x 22 x 2.4 mm) bga 3 chip enables and jtag cy7c1381d-133bzxc cy7c1383d-133bzxc bb165d lead-free 165-ball fine-pitch ball grid array (13 x 15 x 1.4mm) 3 chip enables and jtag 100 cy7c1381d-100axc cy7c1383d-100axc a101 lead-free 100-lead thin quad flat pack (14 x 20 x 1.4mm) 3 chip enables commercial cy7c1381d-100bgc bg119 119-ball (14 x 22 x 2.4 mm) bga 3 chip enables and jtag cy7c1383d-100bgc cy7c1381d-100bzc bb165d 165-ball fine-pitch ball grid array (13 x 15 x 1.4mm) 3 chip enables and jtag cy7c1383d-100bzc cy7c1381d-100bgxc bg119 lead-free 119-ball (14 x 22 x 2.4 mm) bga 3 chip enables and jtag cy7c1383d-100bgxc cy7c1381d-100bzxc bb165d lead-free 165-ball fine-pitch ball grid array (13 x 15 x 1.4mm) 3 chip enables and jtag cy7c1383d-100bzxc notes: 29. device must be deselected when entering zz mode. see cycle desc riptions table for all possible signal conditions to deselect the device. 30. dqs are in high-z when exiting zz sleep mode.
preliminary cy7c1381d cy7c1383d document #: 38-05544 rev. *a page 26 of 29 100 cy7c1381d-100axi a101 lead-free 100-lead thin quad flat pack (14 x 20 x 1.4mm) 3 chip enables industrial cy7c1383d-100axi cy7c1381d-100bgi bg119 119-ball (14 x 22 x 2.4 mm) bga 3 chip enables and jtag cy7c1383d-100bgi cy7c1381d-100bzi bb165d 165-ball fine-pitch ball grid array (13 x 15 x 1.4mm) 3 chip enables and jtag cy7c1383d-100bzi cy7c1381d-100bgxi bg119 lead-free 119-ball (14 x 22 x 2.4 mm) bga 3 chip enables and jtag cy7c1383d-100bgxi cy7c1381d-100bzxi bb165d lead-free 165-ball fine-pitch ball grid array (13 x 15 x 1.4mm) 3 chip enables and jtag cy7c1383d-100bzxi shaded areas contain advance information. plea se contact your local sales representative for availability of these parts. lead-free bg packages (ordering code:bgx) will be available in 2005. ordering information (continued) speed (mhz) ordering code package name part and package type operating range package diagrams dimensions are in millimeters. 0.300.08 0.65 20.000.10 22.000.20 1.400.05 121 1.60 max. 0.05 min. 0.600.15 0 min. 0.25 0-7 (8x) stand-off r 0.08 min. typ. 0.20 max. 0.15 max. 0.20 max. r0.08min. 0.20 max. 14.000.10 16.000.20 0.10 see detail a detail a 1 100 30 31 50 51 80 81 gauge plane 1.00 ref. 0.20 min. seating plane 100-pin thin plastic quad fl atpack (14 x 20 x 1.4 mm) a101 51-85050-*a
preliminary cy7c1381d cy7c1383d document #: 38-05544 rev. *a page 27 of 29 package diagrams (continued) 51-85115-*b 119-lead pbga (14 x 22 x 2.4 mm) bg119
preliminary cy7c1381d cy7c1383d document #: 38-05544 rev. *a page 28 of 29 ? cypress semiconductor corporation, 2004. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. i486 is a trademark, and intel and pentium are registered trademarks, of intel cor poration. powerpc is a trademark of ibm corporation. all product and company names mentioned in th is document are the trademarks of their respective holders. package diagrams (continued) 51-85180-** 165 fbga 13 x 15 x 1.40 mm bb165d
preliminary cy7c1381d cy7c1383d document #: 38-05544 rev. *a page 29 of 29 document history page document title: cy7c1381d/cy7c1383d 18-mbit (512k x 36/1m x 18) flow-through sram document number: 38-05544 rev. ecn no. issue date orig. of change description of change ** 254518 see ecn rkf new data sheet *a 288531 see ecn syt edited descri ption under ?ieee 1149 .1 serial boundary scan (jtag)? for non-compliance with 1149.1 removed 117 mhz speed bin added lead-free information for 100-pin tqfp, 119 bga and 165 fbga package added comment of ?lead-free bg packa ges availability? below the ordering information

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